Kavindra Kandpal
Orcid: 0000-0002-2683-2230
According to our database1,
Kavindra Kandpal
authored at least 15 papers
between 2019 and 2024.
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Bibliography
2024
A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset.
Integr., 2024
2023
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
Comput. Electr. Eng., 2022
Design of a Low-Voltage Charge-Sensitive Preamplifier Interfaced with Piezoelectric Tactile Sensor for Tumour Detection.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
Mechanical strain and bias-stress compensated, 6T-1C pixel circuit for flexible AMOLED displays.
Microelectron. J., 2021
Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications.
J. Circuits Syst. Comput., 2021
2020
Design of threshold voltage insensitive pixel driver circuitry using a-IGZO TFT for AMOLED displays.
Microelectron. J., 2020
J. Circuits Syst. Comput., 2020
Design of a voltage-programmed <i>V</i> <sub>TH</sub> compensating pixel circuit for AMOLED displays using diode-connected a-IGZO TFT.
IET Circuits Devices Syst., 2020
Design of a Threshold Voltage Insensitive 3T1C Pixel Circuit Using a-IGZO TFT for AMOLED Displays.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2019
IIP3 Improvement in Subthreshold LNAs Using Modified Derivative Superposition Technique for IoT Applications.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019