Kaushik Vaidyanathan

According to our database1, Kaushik Vaidyanathan authored at least 10 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Boreas: A Cost-Effective Mitigation Method for Advanced Hotspots using Machine Learning and Hardware Telemetry.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2021
HotGauge: A Methodology for Characterizing Advanced Hotspots in Modern and Next Generation Processors.
Proceedings of the IEEE International Symposium on Workload Characterization, 2021

2018
Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

2015
Exploiting Challenges of Sub-20 nm CMOS for Affordable Technology Scaling.
CoRR, 2015

A synthesis methodology for application-specific logic-in-memory designs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Sub-20 nm design technology co-optimization for standard cell logic.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Efficient and secure intellectual property (IP) design with split fabrication.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Building trusted ICs using split fabrication.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2012
Design Automation Framework for Application-Specific Logic-in-Memory Blocks.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012


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