Kattekola Naresh

According to our database, Kattekola Naresh authored at least 2 papers between 2021 and 2022.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2022

Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor.

Kattekola Naresh, Y. Padma Sai, Shubhankar Majumdar

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2021

Efficient Design of Artificial Neural Networks using Approximate Compressors and Multipliers.

Kattekola Naresh, Shubhankar Majumdar, Y. Padma Sai, P. Rohith Sai

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021