Katsuyuki Sato

According to our database1, Katsuyuki Sato authored at least 5 papers between 1991 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2007
Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2007

1998
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register.
IEEE J. Solid State Circuits, 1998

1996
A 29-ns 64-Mb DRAM with hierarchical array architecture.
IEEE J. Solid State Circuits, 1996

1992
A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array.
IEEE J. Solid State Circuits, November, 1992

1991
A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current.
IEEE J. Solid State Circuits, November, 1991


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