Katsuyuki Ikeuchi
According to our database1,
Katsuyuki Ikeuchi
authored at least 12 papers
between 2008 and 2018.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2018
An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer.
IEEE J. Solid State Circuits, 2018
An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2012
Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and V<sub>TH</sub>-Tuned Oscillator With Fixed Charge Programming.
IEEE J. Solid State Circuits, 2012
2011
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing.
IEEE J. Solid State Circuits, 2011
1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling.
IEICE Trans. Electron., 2011
A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Reduction of minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic circuits with post-fabrication automatically selective charge injection.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node.
Proceedings of the ESSCIRC 2008, 2008