Katsuya Mizumoto

According to our database, Katsuya Mizumoto authored at least 5 papers between 2006 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems.

Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems.

Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2007

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture.

Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto

IEEE J. Solid State Circuits, 2007

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.

Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu

IEEE J. Solid State Circuits, 2007

2006

A 40GOPS 250mW massively parallel processor based on matrix architecture.

Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006