Katsutaka Kimura

According to our database, Katsutaka Kimura authored at least 9 papers between 1993 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2002

A low-impedance open-bitline array for multigigabit DRAM.

Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura

IEEE J. Solid State Circuits, 2002

2001

A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

IEEE J. Solid State Circuits, 2001

1999

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.

Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura

IEEE J. Solid State Circuits, 1999

1998

Internal voltage generator for low voltage, quarter-micrometer flash memories.

Takayuki Kawahara, Syun-ichi Saeki, Yusuke Jyouno, Naoki Miyamoto, Takashi Kobayashi, Katsutaka Kimura

IEEE J. Solid State Circuits, 1998

20-Mb/s erase/record flash memory by asymmetrical operation.

Takayuki Kawahara, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, Katsutaka Kimura

IEEE J. Solid State Circuits, 1998

1997

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory.

Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya

IEEE J. Solid State Circuits, 1997

1996

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories.

Takayuki Kawahara, Takashi Kobayashi, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, T. Adachi, Masataka Kato, Akihiko Sato, J. Yugami, Hitoshi Kume, Katsutaka Kimura

IEEE J. Solid State Circuits, 1996

1995

High reliability electron-ejection method for high density flash memories.

Takayuki Kawahara, Naoki Miyamoto, Syun-ichi Saeki, Yusuke Jyouno, Masataka Kato, Katsutaka Kimura

IEEE J. Solid State Circuits, December, 1995

1993

A single 1.5-V digital chip for a 10⁶ synapse neural network.

Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito

IEEE Trans. Neural Networks, 1993