Katsushi Asahina

According to our database, Katsushi Asahina authored at least 4 papers between 2008 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs.

Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller.

Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato

Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

2009

Low-jitter fractional spread-spectrum clock generator using fast-settling dual charge-pump technique for Serial-ATA application.

Takashi Kawamoto, Tomoaki Takahashi, Shigeyuki Suzuki, Takayuki Noto, Katsushi Asahina

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude.

H. Uchiki, Y. Ota, M. Tani, Yasushi Hayakawa, Katsushi Asahina

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008