Katsuro Sasaki

According to our database, Katsuro Sasaki authored at least 16 papers between 1989 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

Instruction buffering to reduce power in processors for signal processing.

Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki

IEEE Trans. Very Large Scale Integr. Syst., 1997

1996

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.

Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits.

Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome

IEEE J. Solid State Circuits, April, 1995

Half-swing clocking scheme for 75% power saving in clocking circuitry.

Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki

IEEE J. Solid State Circuits, April, 1995

A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.

Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome

IEEE J. Solid State Circuits, March, 1995

Trends in low-power RAM circuit technologies.

Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome

Proc. IEEE, 1995

1994

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers.

Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki

IEEE J. Solid State Circuits, April, 1994

1993

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic.

Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome

IEEE J. Solid State Circuits, November, 1993

A 16-Mb CMOS SRAM with a 2.3- mu m² single-bit-line memory cell.

Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki

IEEE J. Solid State Circuits, November, 1993

1992

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier.

Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu

IEEE J. Solid State Circuits, November, 1992

A 1-V TFT-load SRAM using a two-step word-voltage method.

Koichiro Ishibashi, Koichi Takasugi, Toshiaki Yamanaka, Takashi Hashimoto, Katsuro Sasaki

IEEE J. Solid State Circuits, November, 1992

A 1.5-V full-swing BiCMOS logic circuit.

Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki

IEEE J. Solid State Circuits, November, 1992

A voltage down converter with submicroampere standby current for low-power static RAMs.

Koichiro Ishibashi, Katsuro Sasaki, Hiroshi Toyoshima

IEEE J. Solid State Circuits, June, 1992

A 1.7-V adjustable I/O interface for low-voltage fast SRAMs.

Koichiro Ishibashi, Katsuro Sasaki, Toshiaki Yamanaka, Hiroshi Toyoshima, Fumio Kojima

IEEE J. Solid State Circuits, April, 1992

1990

A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current.

Katsuro Sasaki, Koichiro Ishibashi, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Nobuyuki Moriwake, Shigeru Honjo, Shuji Ikeda, Atsuyoshi Koike, Satoshi Meguro, Osamu Minato

IEEE J. Solid State Circuits, October, 1990

1989

A 9-ns 1-Mbit CMOS SRAM.

Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo

IEEE J. Solid State Circuits, October, 1989