Katsunori Seno

According to our database1, Katsunori Seno authored at least 5 papers between 1989 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1990
1992
1994
1996
1998
2000
2002
2004
0
1
2
1
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2005
Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor.
IEICE Trans. Electron., 2005

1998
Evaluation of a Low-Power Reconfigurable DSP Architecture.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

1993
A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier.
IEEE J. Solid State Circuits, November, 1993

1990
A multibit test trigger circuit for megabit SRAMs.
IEEE J. Solid State Circuits, February, 1990

1989
A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads.
IEEE J. Solid State Circuits, October, 1989


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