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Katsunori Seno

According to our database1, Katsunori Seno authored at least 3 papers between 1989 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2005
Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor.
[BibTeX]
[DOI]
Takahiro Seki
,
Satoshi Akui
,
Katsunori Seno
,
Masakatsu Nakai
,
Tetsumasa Meguro
,
Tetsuo Kondo
,
Akihiko Hashiguchi
,
Hirokazu Kawahara
,
Kazuo Kumano
,
Masayuki Shimura
IEICE Trans. Electron., 2005

1998
Evaluation of a Low-Power Reconfigurable DSP Architecture.
[BibTeX]
[DOI]
Arthur Abnous
,
Katsunori Seno
,
Yuji Ichikawa
,
Marlene Wan
,
Jan M. Rabaey
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

1989
A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads.
[BibTeX]
[DOI]
Fumio Miyaji
,
Yasushi Matsuyama
,
Yoshik Kanaishi
,
Katsunori Seno
,
Takashi Emori
,
Yoshiaki Hagiwara
IEEE J. Solid State Circuits, October, 1989


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