Katsuhiro Shimohigashi

According to our database, Katsuhiro Shimohigashi authored at least 10 papers between 1988 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register.

Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana

IEEE J. Solid State Circuits, 1998

1993

Low-voltage ULSI design.

Katsuhiro Shimohigashi, Koichi Seki

IEEE J. Solid State Circuits, April, 1993

1991

Quasi-complementary BiCMOS for sub-3-V digital circuits.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, November, 1991

1990

A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current.

Katsuro Sasaki, Koichiro Ishibashi, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Nobuyuki Moriwake, Shigeru Honjo, Shuji Ikeda, Atsuyoshi Koike, Satoshi Meguro, Osamu Minato

IEEE J. Solid State Circuits, October, 1990

A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic.

Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu

IEEE J. Solid State Circuits, April, 1990

An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell.

Koichiro Ishibashi, Toshiaki Yamanaka, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, February, 1990

1989

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM.

Makoto Suzuki, Suguru Tachibana, Atsuo Watanabe, Shoji Shukuri, Hisayuki Higuchi, Takahiro Nagano, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, October, 1989

A 9-ns 1-Mbit CMOS SRAM.

Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo

IEEE J. Solid State Circuits, October, 1989

A feedback-type BiCMOS logic gate.

Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Atsuo Watnabe, Shoji Shukuri, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, October, 1989

1988

An experimental large-capacity semiconductor file memory using 16-levels/cell storage.

Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, February, 1988