Katsuhiko Degawa
According to our database1,
Katsuhiko Degawa
authored at least 16 papers
between 2003 and 2015.
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Bibliography
2015
Proceedings of the 2015 IEEE International Test Conference, 2015
2011
Application of a continuous-time level crossing quantization method for timing noise measurements.
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2009
Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
J. Multiple Valued Log. Soft Comput., 2009
Proceedings of the IEEE International Conference on Acoustics, 2009
2008
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
2007
J. Multiple Valued Log. Soft Comput., 2007
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.
J. Multiple Valued Log. Soft Comput., 2007
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
2005
Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects.
J. Multiple Valued Log. Soft Comput., 2005
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
2004
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
2003
Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003