Katsuhiko Degawa

According to our database, Katsuhiko Degawa authored at least 16 papers between 2003 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A new method for measuring alias-free aperture jitter in an ADC output.

Takahiro J. Yamaguchi, Katsuhiko Degawa, Masayuki Kawabata, Masahiro Ishida, Koichiro Uekusa, Mani Soma

Proceedings of the 2015 IEEE International Test Conference, 2015

2011

Application of a continuous-time level crossing quantization method for timing noise measurements.

Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu

Proceedings of the 2011 IEEE International Test Conference, 2011

An equivalent-time and clocked approach for continuous-time quantization.

Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009

Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.

Naofumi Homma, Yuki Watanabe, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

J. Multiple Valued Log. Soft Comput., 2009

Phase-based alignment of two signals having partially overlapped spectra.

Albert Tumewu, Kazuyuki Miyazawa, Takafumi Aoki, Takahiro J. Yamaguchi, Katsuhiko Degawa, Takayuki Akita

Proceedings of the IEEE International Conference on Acoustics, 2009

2008

High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.

Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

2007

Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams.

Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

J. Multiple Valued Log. Soft Comput., 2007

Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi

J. Multiple Valued Log. Soft Comput., 2007

Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.

Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2006

A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

J. Multiple Valued Log. Soft Comput., 2005

A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.

Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi

Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

2004

A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.

Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003

Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003