Katell Morin-Allory

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2021

Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

A High-Level Design Flow for Locally Body Biased Asynchronous Circuits.

[BibT_eX]

[DOI]

Yoan Decoudu

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method.

[BibT_eX]

[DOI]

Noureddine Ait Said

Mounir Benabdenbi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020

From High-Level Synthesis to Bundled-Data Circuits.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

High Level Fault Injection Method for Evaluating Critical System Parameter Ranges.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach.

[BibT_eX]

[DOI]

Noureddine Ait Said

Mounir Benabdenbi

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019

Mining Missing Assumptions from Counter-Examples.

[BibT_eX]

[DOI]

Guillaume Plassan

ACM Trans. Embed. Comput. Syst., 2019

A Distributed Body-Biasing Strategy for Asynchronous Circuits.

[BibT_eX]

[DOI]

Thiago Ferreira de Paiva Leite

Yoan Decoudu

Alexis Rodrigo Iga Jadue

Otto Aureliano Rolloff

M. Diallo

Rodrigo Possamai Bastos

Sylvain Engels

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Comparison of Synchronous and Asynchronous FIR Filter Architectures.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Event-Based Control, 2019

2017

Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Extraction of missing formal assumptions in under-constrained designs.

[BibT_eX]

[DOI]

Guillaume Plassan

Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

2016

Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Conclusively verifying clock-domain crossings in very large hardware designs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Clock domain crossing formal verification: a meta-model.

[BibT_eX]

[DOI]

Mejid Kebaili

Jean-Christophe Brignone

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

2015

Efficient and Correct by Construction Assertion-Based Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Enabler-based synchronizer model for clock domain crossing static verification.

[BibT_eX]

[DOI]

Mejid Kebaili

Jean-Christophe Brignone

Proceedings of the 2015 Forum on Specification and Design Languages, 2015

2013

SyntHorus-2: Automatic prototyping from PSL.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Fast prototyping from assertions: A pragmatic approach.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

2011

C-elements for Hardened Self-timed Circuits.

[BibT_eX]

[DOI]

Florent Ouchet

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Does asynchronous technology bring robustness in synchronous circuit monitoring?

[BibT_eX]

[DOI]

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Formal Verification of C-element Circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

2010

Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Synthesis of asynchronous monitors for critical electronic systems.

[BibT_eX]

[DOI]

Alexandre Porcher

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Delay Insensitivity Does Not Mean Slope Insensitivity!

[BibT_eX]

[DOI]

Florent Ouchet

Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2009

From Assertion-Based Verification to Assertion-Based Synthesis.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

MYGEN: automata-based on-line test generator for assertion-based verification.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

RAT-based formal verification of QDI asynchronous controllers.

[BibT_eX]

[DOI]

Khaled Alsayeg

Proceedings of the Forum on specification and Design Languages, 2009

High-level symbolic simulation for automatic model extraction.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

Assertion-Based Design with Horus.

[BibT_eX]

[DOI]

Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Proving and disproving assertion rewrite rules with automated theorem provers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

2007

Synthesis of Property Monitors for Online Fault Detection.

[BibT_eX]

[DOI]

Eric Gascard

J. Circuits Syst. Comput., 2007

Asynchronous online-monitoring of logical and temporal assertions.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2007

Prototyping Generators for On-line Test Vector Generation Based on PSL Properties.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

On-Line Test Vector Generation from Temporal Constraints Written in PSL.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

Asynchronous Assertion Monitors for multi-Clock Domain System Verification.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

On-line Monitoring of Properties Built on Regular Expressions.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2006

Proven correct monitors from PSL specifications.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Verification of safety properties for parameterized regular systems.

[BibT_eX]

[DOI]

David Cachera

ACM Trans. Embed. Comput. Syst., 2005

A proof of correctness for the construction of property monitors.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic.

[BibT_eX]

[DOI]

David Cachera

Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004

Vérification Formelle dans le Modèle Polyédrique. (Formal Verification in the Polyhedral Model).

[BibT_eX]

[DOI]

PhD thesis, 2004

2003

Verification of Control Properties in the Polyhedral Model.

[BibT_eX]

[DOI]

David Cachera