Katayoun Neshatpour

Orcid: 0000-0002-0094-316X

According to our database1, Katayoun Neshatpour authored at least 19 papers between 2012 and 2020.

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Bibliography

2020
ICNN: The Iterative Convolutional Neural Network.
ACM Trans. Embed. Comput. Syst., 2020

2019
Big vs little core for energy-efficient Hadoop computing.
J. Parallel Distributed Comput., 2019

Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018
Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Hardware Accelerated Mappers for Hadoop MapReduce Streaming.
IEEE Trans. Multi Scale Comput. Syst., 2018

Hadoop Workloads Characterization for Performance and Energy Efficiency Optimizations on Microservers.
IEEE Trans. Multi Scale Comput. Syst., 2018

Energy-efficient acceleration of MapReduce applications using FPGAs.
J. Parallel Distributed Comput., 2018

Architectural considerations for FPGA acceleration of machine learning applications in MapReduce.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Big vs little core for energy-efficient Hadoop computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Big biomedical image processing hardware acceleration: A case study for K-means and image filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Big data analytics on heterogeneous accelerator architectures.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Accelerating Big Data Analytics Using FPGAs.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Accelerating Machine Learning Kernel in Hadoop Using FPGAs.
Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015

Energy-efficient acceleration of big data analytics applications using FPGAs.
Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015

2012
A low-complexity high-throughput ASIC for the SC-FDMA MIMO detectors.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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