Katarina Paulsson

According to our database1, Katarina Paulsson authored at least 17 papers between 2000 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2009
Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems.
Microprocess. Microsystems, 2009

2008
Towards Novel Approaches in Design Automation for FPGA Power Optimization.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization.
Proceedings of the FPL 2008, 2008

Data path driven waveform-like reconfiguration.
Proceedings of the FPL 2008, 2008

Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project.
Proceedings of the FPL 2007, 2007

Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.
Proceedings of the FPL 2007, 2007

2006
On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Physical 2D Morphware and Power Reduction Methods for Everyone.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2000
Learning at work - a combination of experience based learning and theoretical education.
Behav. Inf. Technol., 2000


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