Katarína Jelemenská

According to our database1, Katarína Jelemenská authored at least 13 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2020
Automation of Dynamic Power Management in FPGA-Based Energy-Constrained Systems.
IEEE Access, 2020

2018
Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation.
Integr., 2018

2017
Verification of Power-Management Specification at Early Stages of Power-Constrained Systems Design.
J. Circuits Syst. Comput., 2017

PMS2UPF: An automated transition from ESL to RTL power-intent specification.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Early-stage verification of power-management specification in low-power systems design.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Power-management high-level synthesis.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Power-Management Specification in SystemC.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
Power-efficient power-management logic.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Self-managing power management unit.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
Managing digital-system power at the system level.
Proceedings of the AFRICON 2013, Pointe aux Piments, Mauritius, September 9-12, 2013, 2013

Extensible framework for graphical representation of HDL models and Simulation Results.
Proceedings of the AFRICON 2013, Pointe aux Piments, Mauritius, September 9-12, 2013, 2013

2012
VHDLVisualizer: HDL model visualization with simulation-based verification.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
VHDL structural model visualization.
Proceedings of EUROCON 2011, 2011


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