Kasho Yamamoto

According to our database, Kasho Yamamoto authored at least 6 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions.

Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura

IEEE J. Solid State Circuits, 2021

4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems.

Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems.

Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.

Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

FPGA-Based Annealing Processor with Time-Division Multiplexing.

Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

IEICE Trans. Inf. Syst., 2019

2017

A Time-Division Multiplexing Ising Machine on FPGAs.

Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017