Karthikeyan Lingasubramanian

According to our database, Karthikeyan Lingasubramanian authored at least 16 papers between 2005 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study.

Varsha Kakkara, Karthi Balasubramanian, B. Yamuna, Deepak Mishra, Karthikeyan Lingasubramanian, Senthil Murugan

PeerJ Comput. Sci., 2020

2019

Effect of sign-bit-flipping trojan on turbo coded communication systems.

Karthi Balasubramanian, B. Yamuna, Salija P, Karthikeyan Lingasubramanian, Deepak Mishra

Proceedings of the 20th International Conference on Distributed Computing and Networking, 2019

2018

Study of hardware trojans based security vulnerabilities in cyber physical systems.

Karthikeyan Lingasubramanian, Ranveer Kumar, Nagendra Babu Gunti, Thomas H. Morris

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Effect of hardware Trojans on the performance of a coded communication system.

A. R. Aravind, S. R. Kesavaraman, Karthi Balasubramanian, B. Yamuna, Karthikeyan Lingasubramanian

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2017

Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits.

Gunti Nagendra Babu, Karthikeyan Lingasubramanian

Integr., 2017

Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme.

Nagendra Babu Gunti, Karthikeyan Lingasubramanian

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMR.

Nagendra Babu Gunti, Karthikeyan Lingasubramanian

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2014

Realizing a security aware triple modular redundancy scheme for robust integrated circuits.

Gunti Nagendra Babu, Aman Khatri, Karthikeyan Lingasubramanian

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

2011

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis.

Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja

Microelectron. Reliab., 2011

Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.

Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

2009

Probabilistic Error Modeling for Nano-Domain Logic Circuits.

Thara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja

IEEE Trans. Very Large Scale Integr. Syst., 2009

Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis

Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja

CoRR, 2009

An Error Model to Study the Behavior of Transient Errors in Sequential Circuits.

Karthikeyan Lingasubramanian, Sanjukta Bhanja

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2007

Probabilistic maximum error modeling for unreliable logic circuits.

Karthikeyan Lingasubramanian, Sanjukta Bhanja

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks.

Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan

ACM Trans. Design Autom. Electr. Syst., 2006

2005

Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks.

Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005