Karthik Yogendra
According to our database1,
Karthik Yogendra
authored at least 17 papers
between 2013 and 2017.
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Bibliography
2017
ACM J. Emerg. Technol. Comput. Syst., 2017
Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
2016
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Spintronic devices for ultra-low power neuromorphic computation (Special session paper).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
CoRR, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013