Karthik Ganesan
Orcid: 0000-0002-7559-0928Affiliations:
- Stanford University, CA, USA
According to our database1,
Karthik Ganesan
authored at least 13 papers
between 2011 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2021
Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection.
CoRR, 2021
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
On the Total Power Capacity of Regular-LDPC Codes With Iterative Message-Passing Decoders.
IEEE J. Sel. Areas Commun., 2016
2015
Towards Approaching Total-Power-Capacity: Transmit and Decoding Power Minimization for LDPC Codes.
CoRR, 2015
2012
Proceedings of the 2012 IEEE Global Communications Conference, 2012
Proceedings of the 50th Annual Allerton Conference on Communication, 2012
2011
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the Information Theory and Applications Workshop, 2011