Kartheek Rangineni

According to our database, Kartheek Rangineni authored at least 3 papers between 2018 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators.

Jeff Zhang, Zahra Ghodsi, Siddharth Garg, Kartheek Rangineni

IEEE Des. Test, 2020

2018

ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators.

Jeff Zhang, Kartheek Rangineni, Zahra Ghodsi, Siddharth Garg

CoRR, 2018

Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators.

Jeff Zhang, Kartheek Rangineni, Zahra Ghodsi, Siddharth Garg

Proceedings of the 55th Annual Design Automation Conference, 2018