Karine Heydemann

Orcid: 0000-0003-2092-924X

According to our database1, Karine Heydemann authored at least 50 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2024
Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

2023
MAFIA: Protecting the Microarchitecture of Embedded Systems Against Fault Injection Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

LeakageVerif: Efficient and Scalable Formal Verification of Leakage in Symbolic Expressions.
IEEE Trans. Software Eng., June, 2023

Fault Attacks Sensitivity of Public Parameters in the Dilithium Verification.
IACR Cryptol. ePrint Arch., 2023

A Tale of Resilience: On the Practical Security of Masked Software Implementations.
IEEE Access, 2023

μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections.
Proceedings of the Formal Methods in Computer-Aided Design, 2023

SAMVA: Static Analysis for Multi-fault Attack Paths Determination.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2023

2022
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Armistice: Micro-Architectural Leakage Modelling for Masked Software Formal Verification.
IACR Cryptol. ePrint Arch., 2022

Exploration of Fault Effects on Formal RISC-V Microarchitecture Models.
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2022

SCI-FI: Control Signal, Code, and Control Flow Integrity against Fault Injection Attacks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Reconciling optimization with secure compilation.
Proc. ACM Program. Lang., 2021

Correction to: Editorial about PROOFS 2019.
J. Cryptogr. Eng., 2021

Editorial about PROOFS 2019.
J. Cryptogr. Eng., 2021

LeakageVerif: Scalable and Efficient Leakage Verification in Symbolic Expressions.
IACR Cryptol. ePrint Arch., 2021

Secure Optimization Through Opaque Observations.
CoRR, 2021

2020
Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial Interpolation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Custom Instruction Support for Modular Defense against Side-channel and Fault Attacks.
IACR Cryptol. ePrint Arch., 2020

Processor Anchor to Increase the Robustness Against Fault Injection and Cyber Attacks.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020

Secure delivery of program properties through optimizing compilation.
Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020

2019
Side-channel robustness analysis of masked assembly codes using a symbolic approach.
J. Cryptogr. Eng., 2019

SKIVA: Flexible and Modular Side-channel and Fault Countermeasures.
IACR Cryptol. ePrint Arch., 2019

Studying EM Pulse Effects on Superscalar Microarchitectures at ISA Level.
CoRR, 2019

Formally verified software countermeasures for control-flow integrity of smart card C code.
Comput. Secur., 2019

A First ISA-Level Characterization of EM Pulse Effects on Superscalar Microarchitectures: A Secure Software Perspective.
Proceedings of the 14th International Conference on Availability, Reliability and Security, 2019

2018
Automated software protection for the masses against side-channel attacks.
IACR Cryptol. ePrint Arch., 2018

All paths lead to Rome: Polymorphic Runtime Code Generation for Embedded Systems.
Proceedings of the Fifth Workshop on Cryptography and Security in Computing Systems, 2018

CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Automatic Application of Software Countermeasures Against Physical Attacks.
Proceedings of the Cyber-Physical Systems Security., 2018

2017
Compiler-Assisted Loop Hardening Against Fault Attacks.
ACM Trans. Archit. Code Optim., 2017

Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes.
Proceedings of the PROOFS 2017, 2017

2016
NUMA-aware scheduling and memory allocation for data-flow task-parallel applications.
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

Language-Centric Performance Analysis of OpenMP Programs with Aftermath.
Proceedings of the OpenMP: Memory, Devices, and Tasks, 2016

Interactive visualization of cross-layer performance anomalies in dynamic task-parallel applications and systems.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Scalable Task Parallelism for NUMA: A Uniform Abstraction for Coordinated Scheduling and Memory Management.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Efficient Design and Evaluation of Countermeasures against Fault Attacks Using Formal Verification.
Proceedings of the Smart Card Research and Advanced Applications, 2015

2014
Topology-Aware and Dependence-Aware Scheduling and Memory Allocation for Task-Parallel Languages.
ACM Trans. Archit. Code Optim., 2014

Formal verification of a software countermeasure against instruction skip attacks.
J. Cryptogr. Eng., 2014

Automatic Detection of Performance Anomalies in Task-Parallel Programs.
CoRR, 2014

Experimental evaluation of two software countermeasures against fault attacks.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Software Countermeasures for Control Flow Integrity of Smart Card C Codes.
Proceedings of the Computer Security - ESORICS 2014, 2014

2013
Electromagnetic Fault Injection: Towards a Fault Model on a 32-bit Microcontroller.
Proceedings of the 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2013

2012
High Level Model of Control Flow Attacks for Smart Card Functional Security.
Proceedings of the Seventh International Conference on Availability, 2012

2011
Compression de code pour processeurs haute performance.
Tech. Sci. Informatiques, 2011

Using Runtime Activity to Dynamically Filter Out Inefficient Data Prefetches.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010
A framework to experiment optimizations for real-time and embedded software
CoRR, 2010

Attack model for verification of interval security properties for smart card C codes.
Proceedings of the 2010 Workshop on Programming Languages and Analysis for Security, 2010

2008
Étude de la sensibilité aux jeux de données de la compilation itérative.
Tech. Sci. Informatiques, 2008

2006
UFS: a global trade-off strategy for loop unrolling for VLIW architectures.
Concurr. Comput. Pract. Exp., 2006

2005
A Software-only Compression System for Trading-off Performance and Code Size.
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005


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