Karine Heydemann
Orcid: 0000-0003-2092-924X
According to our database1,
Karine Heydemann
authored at least 50 papers
between 2005 and 2024.
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Bibliography
2024
Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
2023
MAFIA: Protecting the Microarchitecture of Embedded Systems Against Fault Injection Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
LeakageVerif: Efficient and Scalable Formal Verification of Leakage in Symbolic Expressions.
IEEE Trans. Software Eng., June, 2023
IACR Cryptol. ePrint Arch., 2023
IEEE Access, 2023
μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections.
Proceedings of the Formal Methods in Computer-Aided Design, 2023
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2023
2022
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Armistice: Micro-Architectural Leakage Modelling for Masked Software Formal Verification.
IACR Cryptol. ePrint Arch., 2022
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2022
SCI-FI: Control Signal, Code, and Control Flow Integrity against Fault Injection Attacks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
IACR Cryptol. ePrint Arch., 2021
2020
Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial Interpolation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Custom Instruction Support for Modular Defense against Side-channel and Fault Attacks.
IACR Cryptol. ePrint Arch., 2020
Processor Anchor to Increase the Robustness Against Fault Injection and Cyber Attacks.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020
Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020
2019
J. Cryptogr. Eng., 2019
IACR Cryptol. ePrint Arch., 2019
Formally verified software countermeasures for control-flow integrity of smart card C code.
Comput. Secur., 2019
A First ISA-Level Characterization of EM Pulse Effects on Superscalar Microarchitectures: A Secure Software Perspective.
Proceedings of the 14th International Conference on Availability, Reliability and Security, 2019
2018
IACR Cryptol. ePrint Arch., 2018
Proceedings of the Fifth Workshop on Cryptography and Security in Computing Systems, 2018
CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the Cyber-Physical Systems Security., 2018
2017
ACM Trans. Archit. Code Optim., 2017
Proceedings of the PROOFS 2017, 2017
2016
NUMA-aware scheduling and memory allocation for data-flow task-parallel applications.
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016
Proceedings of the OpenMP: Memory, Devices, and Tasks, 2016
Interactive visualization of cross-layer performance anomalies in dynamic task-parallel applications and systems.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Scalable Task Parallelism for NUMA: A Uniform Abstraction for Coordinated Scheduling and Memory Management.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016
2015
Efficient Design and Evaluation of Countermeasures against Fault Attacks Using Formal Verification.
Proceedings of the Smart Card Research and Advanced Applications, 2015
2014
Topology-Aware and Dependence-Aware Scheduling and Memory Allocation for Task-Parallel Languages.
ACM Trans. Archit. Code Optim., 2014
J. Cryptogr. Eng., 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the Computer Security - ESORICS 2014, 2014
2013
Proceedings of the 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2013
2012
Proceedings of the Seventh International Conference on Availability, 2012
2011
Tech. Sci. Informatiques, 2011
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011
2010
CoRR, 2010
Attack model for verification of interval security properties for smart card C codes.
Proceedings of the 2010 Workshop on Programming Languages and Analysis for Security, 2010
2008
Tech. Sci. Informatiques, 2008
2006
Concurr. Comput. Pract. Exp., 2006
2005
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005