Kari Tiensyrjä

According to our database, Kari Tiensyrjä authored at least 26 papers between 1988 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Early-phase performance exploration of embedded systems with ABSOLUT framework.

Janne Vatjus Anttila, Jari Kreku, Juha Korpi, Subayal Khan, Jukka Saastamoinen, Kari Tiensyrjä

J. Syst. Archit., 2013

2011

System Level Performance Simulation of Distributed GENESYS Applications on Multi-core Platforms.

Subayal Aftab Khan, Jukka Saastamoinen, Kari Tiensyrjä, Jari Nurmi

Proceedings of the IEEE Ninth International Conference on Dependable, 2011

Multi-threading support for system-level performance simulation of multi-core architectures.

Jukka Saastamoinen, Subayal Khan, Kari Tiensyrjä, Tapio Taipale

Proceedings of the ARCS 2011, 2011

2010

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach.

Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

The MOSART Mapping Optimization for Multi-Core ARchiTectures.

Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

From Y-chart to seamless integration of application design and performance simulation.

Subayal Khan, Eila Ovaska, Kari Tiensyrjä, Jari Nurmi

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile.

Subayal Khan, Kari Tiensyrjä, Jari Nurmi

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Automatic workload generation for system-level exploration based on modified GCC compiler.

Jari Kreku, Kari Tiensyrjä, Geert Vanmeerbeeck

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Linking GENESYS application architecture modelling with platform performance simulation.

Subayal Khan, Susanna Pantsar-Syväniemi, Jari Kreku, Kari Tiensyrjä, Juha-Pekka Soininen

Proceedings of the Forum on specification and Design Languages, 2009

2008

Design Flow Instantiation for Run-Time Reconfigurable Systems: A Case Study.

Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi

EURASIP J. Embed. Syst., 2008

Combining UML2 Application and SystemC Platform Modelling for Performance Evaluation of Real-Time Embedded Systems.

Jari Kreku, Mika Hoppari, Tuomo Kestilä, Yang Qu, Juha-Pekka Soininen, Per Andersson, Kari Tiensyrjä

EURASIP J. Embed. Syst., 2008

Application Workload and SystemC Platform Modeling for Performance Evaluation.

Jari Kreku, Mika Hoppari, Tuomo Kestilä, Yang Qu, Juha-Pekka Soininen, Kari Tiensyrjä

Proceedings of the Languages for Embedded Systems and their Applications, 2008

Application - Platform Performance Modeling and Evaluation.

Jari Kreku, Mika Hoppari, Tuomo Kestilä, Yang Qu, Juha-Pekka Soininen, Kari Tiensyrjä

Proceedings of the Forum on specification and Design Languages, 2008

2007

System-Level Design for Partially Reconfigurable Hardware.

Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

SystemC workload model generation from UML for performance simulation.

Jari Kreku, Mika Hoppari, Kari Tiensyrjä, Per Andersson

Proceedings of the Forum on specification and Design Languages, 2007

2006

System Level Architecture Exploration for Reconfigurable Systems On Chip.

Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Layered UML Workload and SystemC Platform Models.

Jari Kreku, Yang Qu, Juha-Pekka Soininen, Kari Tiensyrjä

Proceedings of the Forum on specification and Design Languages, 2006

2005

SystemC-based Design Methodology for Reconfigurable System-on-Chip.

Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

System-Level Modeling of Dynamically Reconfigurable Co-processors.

Yang Qu, Kari Tiensyrjä, Kostas Masselos

Proceedings of the Field Programmable Logic and Application, 2004

SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip.

Kari Tiensyrjä, Miroslav Cupák, Kostas Masselos, Marko Pettissalo

Proceedings of the Forum on specification and Design Languages, 2004

2002

A Network on Chip Architecture and Design Methodology.

Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

1997

Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models.

Sien-An Ong, Kari Tiensyrjä, Lech Józwiak

Proceedings of the 23rd EUROMICRO Conference '97, 1997

1995

Cosimulation of real-time control systems.

Juha-Pekka Soininen, Tuomo Huttunen, Kari Tiensyrjä, Hannu Heusala

Proceedings of the Proceedings EURO-DAC'95, 1995

1994

Boundary Scan Testing Combined with Power Supply Current Monitoring.

Matti Kärkkäinen, Kari Tiensyrjä, Matti Weissenfelt

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1989

SW/HW-partitioning of real-time embedded systems.

Juha-Pekka Soininen, Matti Sipola, Kari Tiensyrjä

Microprocessing and Microprogramming, 1989

1988

Real-time structured analysis in system level design of embedded ASICs.

Timo Juntunen, Jorma Kivelä, Auli Reinikka, Matti Sipola, Juha-Pekka Soininen, Kari Tiensyrjä, Tuomo Tikkanen

Microprocess. Microprogramming, 1988