Kari Hepola

According to our database, Kari Hepola authored at least 8 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode.

Kari Hepola, Joonas Multanen, Pekka Jääskeläinen

IEEE Trans. Computers, February, 2024

Cycle Count Estimation of VLIW Processors Using Machine Learning.

Kari Hepola, Jatan Shrestha, Joonas Multanen, Vivienne Wang, Joni Pajarinen, Pekka Jääskeläinen

Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom Instructions.

Kari Hepola, Tharaka Ranasinghe Arachchige, Joonas Multanen, Pekka Jääskeläinen

Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

2023

AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors.

Alex Hirvonen, Topi Leppänen, Kari Hepola, Joonas Multanen, Joost Hoozemans, Pekka Jääskeläinen

J. Signal Process. Syst., September, 2023

2022

Energy-Efficient Instruction Delivery in Embedded Systems With Domain Wall Memory.

Joonas Multanen, Kari Hepola, Asif Ali Khan, Jerónimo Castrillón, Pekka Jääskeläinen

IEEE Trans. Computers, 2022

OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors.

Kari Hepola, Joonas Multanen, Pekka Jääskeläinen

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism.

Kari Hepola, Joonas Multanen, Pekka Jääskeläinen

Proceedings of the Architecture of Computing Systems - 35th International Conference, 2022

2020

Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency.

Joonas Multanen, Kari Hepola, Pekka Jääskeläinen

Proceedings of the 38th IEEE International Conference on Computer Design, 2020