Karen Scheir

According to our database1, Karen Scheir authored at least 8 papers between 2007 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

A 40 nm LP CMOS PLL for high-speed mm-wave communication.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A 57-to-66GHz quadrature PLL in 45nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2008

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
The Potential of FinFETs for Analog and RF Circuit Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007


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