Karen Amirkhanyan

According to our database, Karen Amirkhanyan authored at least 5 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Testing for Electromigration in Sub-5-nm FinFET Memories.

Mahta Mayahinia, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Karen Amirkhanyan, Artur Ghukasyan, Gurgen Harutyunyan, Yervant Zorian

IEEE Des. Test, December, 2024

2022

An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories.

Mahta Mayahinia, Mehdi B. Tahoori, Gurgen Harutyunyan, Grigor Tshagharyan, Karen Amirkhanyan

Proceedings of the IEEE International Test Conference, 2022

2019

On a Method for Segmentation of Memory Instances with Row Redundancies.

Karen Amirkhanyan, Valery A. Vardanian

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

2013

Application of defect injection flow for fault validation in memories.

K. Amirkhanyan, A. Davtyan, Gurgen Harutyunyan, T. Melkumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian

Proceedings of the East-West Design & Test Symposium, 2013

2005

Impact of Soft Error Challenge on SoC Design.

Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005