Karam S. Chatha
Affiliations:- Arizona State University, Tempe, Arizona, USA
According to our database1,
Karam S. Chatha
authored at least 69 papers
between 1998 and 2014.
Collaborative distances:
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on eas.asu.edu
On csauthors.net:
Bibliography
2014
IEEE Trans. Computers, 2014
IEEE Embed. Syst. Lett., 2014
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014
2013
Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors.
ACM Trans. Embed. Comput. Syst., 2013
2012
System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011
Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming.
Proceedings of the 48th Design Automation Conference, 2011
2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Scheduling of synchronous data flow models on scratchpad memory based embedded processors.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Compilation of stream programs for multicore processors that incorporate scratchpad memories.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
A performance model and code overlay generator for scratchpad enhanced embedded processors.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Comput. Electr. Eng., 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Performance optimal speed control of multi-core processors under thermal constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
Throughput optimal task allocation under thermal constraints for multi-core processors.
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Power reduction via macroblock prioritization for power aware H.264 video applications.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
ILP and heuristic techniques for system-level design on network processor architectures.
ACM Trans. Design Autom. Electr. Syst., 2007
Multim. Tools Appl., 2007
Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints.
Integr., 2007
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
An ILP formulation for system-level application mapping on network processor architectures.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures.
Proceedings of the 44th Design Automation Conference, 2007
Performance and resource optimization of NoC router architecture for master and slave IP cores.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Smart driver for power reduction in next generation bistable electrophoretic display technology.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Proceedings of the Image and Video Retrieval, 5th International Conference, 2006
2005
Quality-of-service and error control techniques for mesh-based network-on-chip architectures.
Integr., 2005
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 13th ACM International Conference on Multimedia, 2005
System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
An automated technique for topology and route generation of application specific on-chip interconnection networks.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 12th ACM International Conference on Multimedia, 2004
Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures.
Proceedings of the MIS 2004, 2004
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 2004 Design, 2004
2002
Hardware-software partitioning and pipelined scheduling of transformative applications.
IEEE Trans. Very Large Scale Integr. Syst., 2002
2001
MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
2000
An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling.
Des. Autom. Embed. Syst., 2000
1999
An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999
1998
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998
Proceedings of the 11th International Symposium on System Synthesis, 1998
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998