Kanupriya Gulati

According to our database, Kanupriya Gulati authored at least 30 papers between 2005 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2013

Using GPUs to Accelerate CAD Algorithms.

John F. Croix, Sunil P. Khatri, Kanupriya Gulati

IEEE Des. Test, 2013

2010

Fault Table Computation on GPUs.

Kanupriya Gulati, Sunil P. Khatri

J. Electron. Test., 2010

Boolean satisfiability on a graphics processor.

Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

FPGA-based hardware acceleration for Boolean satisfiability.

Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas

ACM Trans. Design Autom. Electr. Syst., 2009

Selective Forward Body Bias for High Speed and Low Power SRAMs.

Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri

J. Low Power Electron., 2009

Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation.

Srikanth Alaparthi, Kanupriya Gulati, Sunil P. Khatri

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

On-chip bidirectional wiring for heavily pipelined systems using network coding.

Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 27th International Conference on Computer Design, 2009

Fault table generation using Graphics Processing Units.

Kanupriya Gulati, Sunil P. Khatri

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Robust window-based multi-node technology-independent logic minimization.

Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Low power and high performance sram design using bank-based selective forward body bias.

Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Closed-loop modeling of power and temperature profiles of FPGAs.

Kanupriya Gulati, Sunil P. Khatri, Peng Li

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Accelerating statistical static timing analysis using graphics processing units.

Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Fast circuit simulation on graphics processing units.

Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Highly parallel decoding of space-time codes on graphics processing units.

Kalyana C. Bollapalli, Yiyue Wu, Kanupriya Gulati, Sunil P. Khatri, A. Robert Calderbank

Proceedings of the 47th Annual Allerton Conference on Communication, 2009

2008

SAT-based ATPG using multilevel compatible don't-cares.

Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri

ACM Trans. Design Autom. Electr. Syst., 2008

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations.

Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker

Integr., 2008

Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction.

Kanupriya Gulati, Mandar Waghmode, Sunil P. Khatri, Weiping Shi

IET Comput. Digit. Tech., 2008

Improving FPGA routability using network coding.

Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Towards acceleration of fault simulation using graphics processing units.

Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 45th Design Automation Conference, 2008

2007

A Structured ASIC Design Approach Using Pass Transistor Logic.

Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Toggle Equivalence Preserving (TEP) Logic Optimization.

Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

On Complexity of Internal and External Equivalence Checking.

Eugene Goldberg, Kanupriya Gulati

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

Efficient don't care computation for hierarchical designs.

Kanupriya Gulati, M. Lovell, Sunil P. Khatri

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A probabilistic method to determine the minimum leakage vector for combinational designs.

Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Memory-based crosstalk canceling CODECs for on-chip buses.

Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An Efficient, Scalable Hardware Engine for Boolean SATisfiability.

Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Network coding for routability improvement in VLSI.

Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A design flow to optimize circuit delay by using standard cells and PLAs.

Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Controlling inductive cross-talk and power in off-chip buses using CODECs.

Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.

Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005