Kannan Krishna

According to our database1, Kannan Krishna authored at least 5 papers between 1995 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2006
A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture.
IEEE J. Solid State Circuits, 2005

2002
Spatial averaging and ordering in matched element arrays.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1995
The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

A novel methodology for statistical parameter extraction.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995


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