Kanji Hirabayashi

According to our database, Kanji Hirabayashi authored at least 10 papers between 1984 and 2001.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of four.

2001

An Algebraic Approach to Formal Verification of Microprocessors.

Kanji Hirabayashi

J. Electron. Test., 2001

1998

A Method of Formal Verification of Cryptographic Circuits.

Kanji Hirabayashi

J. Electron. Test., 1998

1996

Hazard simulation of sequential circuits.

Kanji Hirabayashi

J. Electron. Test., 1996

1995

A parametric yield model.

Kanji Hirabayashi

J. Electron. Test., 1995

1993

Delay fault simulation of sequential circuits.

Kanji Hirabayashi

J. Electron. Test., 1993

1991

Self-checking CMOS circuits using pass-transistor logic.

Kanji Hirabayashi

J. Electron. Test., 1991

1990

Probabilistic fault grading based on activation checking and observability analysis.

Masahisa Nakazawa, Susumu Nitta, Kanji Hirabayashi

J. Electron. Test., 1990

1985

Test generation by activation and defect-drive (TEGAD).

Susumu Nitta, Masahiko Kawamura, Kanji Hirabayashi

Integr., 1985

AFS : An Approximate Fault Simulator.

Masahiko Kawamura, Kanji Hirabayashi

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

Functional verification of memory circuits from mask artwork data.

Masahiko Kawamura, Haruo Takagi, Kanji Hirabayashi

Proceedings of the 21st Design Automation Conference, 1984