Kanishkan Vadivel

Orcid: 0000-0003-4186-9530

According to our database1, Kanishkan Vadivel authored at least 13 papers between 2017 and 2024.

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Bibliography

2024
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA.
ACM Trans. Reconfigurable Technol. Syst., June, 2024

TRIP: Trainable Region-of-Interest Prediction for Hardware-Efficient Neuromorphic Processing on Event-based Vision.
CoRR, 2024

EON-1: A Brain-Inspired Processor for Near-Sensor Extreme Edge Online Feature Extraction.
CoRR, 2024

SENSIM: An Event-driven Parallel Simulator for Multi-core Neuromorphic Systems.
Proceedings of the International Joint Conference on Neural Networks, 2024

2022
Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

SACA: System-level Analog CIM Accelerators Simulation Framework: Accurate Simulation of Non-Ideal Components.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2020
System Simulation of Memristor Based Computation in Memory Platforms.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

PET-to-MLIR: A polyhedral front-end for MLIR.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

TDO-CIM: Transparent Detection and Offloading for Computation In-memory.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Towards Efficient Code Generation for Exposed Datapath Architectures.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

CIM-SIM: Computation In Memory SIMuIator.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

2017
Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable Architectures.
Proceedings of the Euromicro Conference on Digital System Design, 2017


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