Kangmin Lee

According to our database1, Kangmin Lee authored at least 18 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Timing offset independent PSCCH detection method for 5G-NR V2X SL systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2018
ParaTM: Transparent Embedding of Hardware Transactional Memory for Traditional Applications.
IEEE Access, 2018

2013
MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2006
Low-power network-on-chip for high-performance SoC design.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A 372 ps 64-bit adder using fast pull-up logic in 0.18µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Packet-switched on-chip interconnection network for system-on-chip applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Analysis and Implementation of Practical, Cost-Effective Networks on Chips.
IEEE Des. Test Comput., 2005

A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Low energy transmission coding for on-chip serial communications.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

On-chip network based embedded core testing.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

SILENT: serialized low energy transmission coding for on-chip interconnection networks.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output buffer.
Proceedings of the ESSCIRC 2003, 2003

A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks.
Proceedings of the ESSCIRC 2003, 2003

A distributed crossbar switch scheduler for on-chip networks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A practical method to use eDRAM in the shared bus packet switch.
Proceedings of the Global Telecommunications Conference, 2002

2001
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications.
IEEE J. Solid State Circuits, 2001

A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001


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