Kanglin Xiao

According to our database, Kanglin Xiao authored at least 15 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations.

Kanglin Xiao, Xin Qiao, Xiaoxin Cui, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model.

Kefei Liu, Jingjie Shang, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Kanglin Xiao, Yi Zhong, Yuan Wang

IEEE Trans. Cogn. Dev. Syst., June, 2024

2023

A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation.

Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips.

Kefei Liu, Xiaoxin Cui, Xiang Ji, Yisong Kuang, Chenglong Zou, Yi Zhong, Kanglin Xiao, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

2022

A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications.

Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang

Microelectron. J., 2022

A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation.

Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Nanbing Pan, Xin'an Wang, Yuan Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro.

Nanbing Pan, Xiaoxin Cui, Xin Qiao, Kanglin Xiao, Qingyu Guo, Yuan Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations.

Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A Full-Neuron Memory Model Designed for Neuromorphic Systems.

Kefei Liu, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Yi Zhong, Kanglin Xiao, Yuan Wang

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Design and Implementation of a Temperature Self-Compensation Balanced Hybrid Ring Oscillator BHRO.

Kanglin Xiao, Bo Wang, Changpei Qiu, Xin'an Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor.

Kanglin Xiao, Xiaoxin Cui, Kefei Liu, Xiaole Cui, Xin'an Wang

Proceedings of the International Joint Conference on Neural Networks, 2021

2019

BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead.

Jiexian Ge, Xiaoxin Cui, Kanglin Xiao, Chenglong Zou, Yi-Hsiang Chen, Rongshan Wei

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing.

Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A balanced hybrid ring oscillator for precise temperature compensation.

Kanglin Xiao, Bo Wang, Xiaoqi Lin, Changpei Qiu

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A multi-phase detecting method for spurs cancellation in all digital fractional-N phase-lock loops.

Tingbing Ouyang, Kanglin Xiao, Xiaoqi Lin, Changpei Qiu, Bo Wang

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018