Kang L. Wang

Orcid: 0000-0002-9363-1279

According to our database1, Kang L. Wang authored at least 44 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Unitary Multi-Margin BERT for Robust Natural Language Processing.
CoRR, 2024

Voltage-Controlled Magnetoelectric Devices for Neuromorphic Diffusion Process.
CoRR, 2024

2023
Proximity-induced magnetic order in topological insulator on ferromagnetic semiconductor.
Sci. China Inf. Sci., December, 2023

Analytical Array-Level Comparison of Read/Write Performance Between Voltage Controlled-MRAM and STT-MRAM.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022
Cryogenic in-memory computing using tunable chiral edge states.
CoRR, 2022

A Multi-domain Magneto Tunnel Junction for Racetrack Nanowire Strips.
CoRR, 2022

2021
Adaptive MRAM Write and Read with MTJ Variation Monitor.
IEEE Trans. Emerg. Top. Comput., 2021

Max and Coincidence Neurons in Neural Networks.
CoRR, 2021

Deep Convolutional Neural Networks with Unitary Weights.
CoRR, 2021

A Thermodynamic Core using Voltage-Controlled Spin-Orbit-Torque Magnetic Tunnel Junctions.
CoRR, 2021

Deep Unitary Convolutional Neural Networks.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020
A 2-D Calibration Scheme for Resistive Nonvolatile Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Criticality or Supersymmetry Breaking?
Symmetry, 2020

2019
Dynamic $(\mathrm{Bi}_{\mathrm{x}}\mathrm{Sb}_{1-\mathrm{x}})_{2}\mathrm{Te}_{\mathrm{3}}$ Synaptic Devices with Programmable Spatio-Temporal Responses.
Proceedings of the Device Research Conference, 2019

2018
A Basic Phase Diagram of Neuronal Dynamics.
Neural Comput., 2018

Recent Progress in Spintronics and Devices.
Proceedings of the 76th Device Research Conference, 2018

Large Room Temperature Charge-to-Spin Conversion Efficiency in Topological Insulator/CoFeB bilayers.
Proceedings of the 76th Device Research Conference, 2018

2017
A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Electric-Field Control of Spin-Orbit Interaction for Low-Power Spintronics.
Proc. IEEE, 2016

Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Ultra-low-power, high-density spintronic programmable logic (SPL).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

MTJ variation monitor-assisted adaptive MRAM write.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2014
Impact of microstrip width and annealing time on the characteristics of micro-scale graphene FETs.
Proceedings of the 37th International Convention on Information and Communication Technology, 2014

2013
Variability Effects in Graphene: Challenges and Opportunities for Device Engineering and Applications.
Proc. IEEE, 2013

2012
Molecular Rotors as Switches.
Sensors, 2012


Effects of disorder on transport properties of extremely scaled graphene nanoribbons.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011
Spin wave functions nanofabric update.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

2010
Towards logic functions as the device.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

2008
Nanoarchitectonics for Heterogeneous Integrated Nanosystems.
Proc. IEEE, 2008

On Power Dissipation in Information Processing.
Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008

Spin Wave Logic Circuit on Silicon Platform.
Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008

Design and defect tolerance beyond CMOS.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
Ge/Si Self-Assembled Quantum Dots and Their Optoelectronic Device Applications.
Proc. IEEE, 2007

The spin-wave nanoscale reconfigurable mesh and the labeling problem.
ACM J. Emerg. Technol. Comput. Syst., 2007

Cellular Nonlinear Network with Spin Wave Bus.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

2006
Size dependence of hall mobility and dislocation density in Ge heteroepitaxial layers grown by MBE on a SiO<sub>2</sub> patterned Si template.
Microelectron. J., 2006

Nano Logic Circuits with Spin Wave Bus.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

A nano-scale reconfigurable mesh with spin waves.
Proceedings of the Third Conference on Computing Frontiers, 2006

Hierarchical Multi-Scale Architectures with Spin Waves.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Molecular and Nanoscale Computing and Technology.
Proceedings of the Handbook of Nature-Inspired and Innovative Computing, 2006

1998
Implementation of Quantum Controlled-NOT Gates Using Asymmetric Semiconductor Quantum Dots.
Proceedings of the Quantum Computing and Quantum Communications, 1998


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