Kang-Il Cho

Orcid: 0000-0003-2791-5422

According to our database1, Kang-Il Cho authored at least 19 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A High Holding Voltage Diode-Triggered SCR for Low-Voltage ESD Application.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

A CMOS Analog Front-End for Hall Sensor Readout IC.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023
A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

2021
A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications.
IEEE J. Solid State Circuits, 2021

A 0.9V 0.022mm<sup>2</sup> 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique.
Proceedings of the International SoC Design Conference, 2020

A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019
A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application.
Proceedings of the 2019 International SoC Design Conference, 2019

A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators.
IEEE J. Solid State Circuits, 2018

A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture.
IEICE Electron. Express, 2018

2017
A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique.
IEICE Electron. Express, 2017

Analog front-end for EMG acquisition system.
Proceedings of the International SoC Design Conference, 2017

A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2012
A digitally enhanced low-distortion delta-sigma modulator for wideband application.
Proceedings of the International SoC Design Conference, 2012

A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011


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