Kaneyoshi Takeshita

According to our database, Kaneyoshi Takeshita authored at least 2 papers between 2001 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output.

Takashi Masuda, Hideyuki Suzuki, Hiroshi Iizuka, Akio Igarashi, Kaneyoshi Takeshita, Takayuki Mogi, Takayuki Shoji, Jeremy Chatwin, Iain Butler, Derek Mellor

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2001

Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS.

Hajime Nakayama, Pin Su, Chenming Hu, Motoaki Nakamura, Hiroshi Komatsu, Kaneyoshi Takeshita, Yasutoshi Komatsu

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001