Kaname Teranishi

According to our database, Kaname Teranishi authored at least 4 papers between 1998 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.

Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Takeshi Kataoka, Toshihiro Hattori

IEEE Micro, 2013

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.

Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

1998

Design and evaluation of a digit-parallel multiple-valued content-addressable memory.

Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama

Syst. Comput. Jpn., 1998

Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI.

Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998