Kanak Agarwal

Proceedings of the 2014 IEEE International Conference on Web Services, 2014

2013

Layout Decomposition and Legalization for Double-Patterning Technology.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A high-speed and large-scale dictionary matching engine for Information Extraction systems.

[BibT_eX]

[DOI]

Raphael Polig

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

Design-aware lithography.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Design driven patterning optimizations for low K1 lithography.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Design-patterning co-optimization of SRAM robustness for double patterning lithography.

[BibT_eX]

[DOI]

Vivek Joshi

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Measuring within-die spatial variation profile through power supply current measurements.

[BibT_eX]

[DOI]

Jim Plusquellic

Dhruva Acharyya

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Coupling timing objectives with optical proximity correction for improved timing yield.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Accelerated statistical simulation via on-demand Hermite spline interpolations.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A framework for double patterning-enabled design.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

Electrically-driven retargeting for nanoscale layouts.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Mechanical Stress Aware Optimization for Leakage Power Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Leveraging existing power control circuits and power delivery architecture for variability measurement.

[BibT_eX]

[DOI]

Dhruva Acharyya

Jim Plusquellic

Proceedings of the 2011 IEEE International Test Conference, 2010

Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices.

[BibT_eX]

[DOI]

Vivek Joshi

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Active learning framework for post-silicon variation extraction and test cost reduction.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Analysis and optimization of SRAM robustness for double patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

SMATO: Simultaneous mask and target optimization for improving lithographic process window.

[BibT_eX]

[DOI]

Michael Orshansky

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

On-die sensors for measuring process and environmental variations in integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A methodology for propagating design tolerances to shape tolerances for use in manufacturing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Closed-form modeling of layout-dependent mechanical stress.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Frequency domain decomposition of layouts for double dipole lithography.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects.

[BibT_eX]

[DOI]

Michael Orshansky

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Analyzing electrical effects of RTA-driven local anneal temperature variation.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

The impact of BEOL lithography effects on the SRAM cell performance and yield.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Characterizing within-die variation from multiple supply port IDDQ measurements.

[BibT_eX]

[DOI]

Dhruva Acharyya

Jim Plusquellic

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Variability in nanometer CMOS: Impact, analysis, and minimization.

[BibT_eX]

[DOI]

Saumil Shah

Integr., 2008

A Design Model for Random Process Variability.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Stress aware layout optimization.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

Leakage power reduction using stress-enhanced layouts.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Characterization and design for variability and reliability.

[BibT_eX]

[DOI]

Kevin J. Nowka

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Parametric Yield Analysis and Optimization in Leakage Dominated Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Dynamic Power Management by Combination of Dual Static Supply Voltages.

[BibT_eX]

[DOI]

Kevin J. Nowka

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Efficient computation of current flow in signal wires for reliability analysis.

[BibT_eX]

[DOI]

Frank Liu

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Rigorous extraction of process variations for 65nm CMOS design.

[BibT_eX]

[DOI]

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Characterizing Process Variation in Nanometer CMOS.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Modeling and analysis of crosstalk noise in coupled RLC interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Statistical interconnect metrics for physical-design optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Power Gating with Multiple Sleep Modes.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Methods for estimating decoupling capacitance of nonswitching circuit blocks.

[BibT_eX]

[DOI]

Emrah Acar

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Characterization of total chip leakage using inverse (reciprocal) gamma distribution.

[BibT_eX]

[DOI]

Emrah Acar

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Statistical analysis of SRAM cell stability.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power-aware global signaling strategies.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Achieving continuous V<sub>T</sub> performance in a dual V<sub>T</sub> process.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Statistical modeling of cross-coupling effects in VLSI interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A simple metric for slew rate of RC circuits based on two circuit moments.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A library compatible driver output model for on-chip RLC transmission lines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Approaches to run-time and standby mode leakage reduction in global buses.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters.

[BibT_eX]

[DOI]

Saumil Shah

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Variational delay metrics for interconnect timing analysis.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

A simplified transmission-line based crosstalk noise model for on-chip RLC wiring.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Dynamic clamping: on-chip dynamic shielding and termination for high-speed RLC buses.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on System-on-Chip, 2003

Optimal Inductance for On-chip RLC Interconnections.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Simple metrics for slew rate of RC circuits based on two circuit moments.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

An effective capacitance based driver output model for on-chip RLC interconnects.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

A library compatible driving point model for on-chip RLC interconnects.

[BibT_eX]

[DOI]