Kanad Ghose

Orcid: 0000-0002-5509-6543

According to our database1, Kanad Ghose authored at least 114 papers between 1988 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Verifiable Sustainability in Data Centers.
CoRR, 2023

Control Flow and Pointer Integrity Enforcement in a Secure Tagged Architecture.
Proceedings of the 44th IEEE Symposium on Security and Privacy, 2023

Thermally-Aware Multi-Core Chiplet Stacking.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
Generic Tagging for RISC-V Binaries.
CoRR, 2022

2021
Deep Learning for Morphological Arrhythmia Classification in Encoded ECG Signal.
Proceedings of the 20th IEEE International Conference on Machine Learning and Applications, 2021

Latency-Aware Dynamic Server and Cooling Capacity Provisioner for Data Centers.
Proceedings of the SoCC '21: ACM Symposium on Cloud Computing, 2021

2020
Heart Monitor Using Flexible Capacitive ECG Electrodes.
IEEE Trans. Instrum. Meas., 2020

Low-Power Discreetly-Wearable Smart ECG Patch with On-Board Analytics.
Proceedings of the 2020 IEEE International Symposium on Medical Measurements and Applications, 2020

2019
A Convolutional Neural Network Feature Detection Approach to Autonomous Quadrotor Indoor Navigation.
Proceedings of the 2019 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2019

Characterization of Liquid Cooled Cold Plates for a Multi Chip Module (MCM) and their Impact on Data Center Chiller Operation.
Proceedings of the 17th IEEE International Conference on Industrial Informatics, 2019

Flow Disruptions and Mitigation in Virtualized Water-Cooled Data Centers.
Proceedings of the 17th IEEE International Conference on Industrial Informatics, 2019

AC vs. Hybrid AC/DC Powered Data Centers: A Workload Based Perspective.
Proceedings of the 17th IEEE International Conference on Industrial Informatics, 2019

Cache-Aware Dynamic Classification and Scheduling for Linux.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

An Adaptive Approach for Dealing with Flow Disruption in Virtualized Water-Cooled Data Centers.
Proceedings of the 12th IEEE International Conference on Cloud Computing, 2019

2015
FlexCore: A Reconfigurable Processor Supporting Flexible, Dynamic Morphing.
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

2014
Continuous, Low Overhead, Run-Time Validation of Program Executions.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013
Run-time control flow authentication: an assessment on contemporary x86 platforms.
Proceedings of the 28th Annual ACM Symposium on Applied Computing, 2013

A group-commit mechanism for ROB-based processors implementing the X86 ISA.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
Detecting and Tracking Coordinated Groups in Dense, Systematically Moving, Crowds.
Proceedings of the Twelfth SIAM International Conference on Data Mining, 2012

Energy-Aware Load Direction for Servers: A Feasibility Study.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

2011
MARSS: a full system simulator for multicore x86 CPUs.
Proceedings of the 48th Design Automation Conference, 2011

2010
Efficiently detecting clusters of mobile objects in the presence of dense noise.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

2009
MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches.
SIGARCH Comput. Archit. News, 2009

An energy-efficient checkpointing mechanism for out of order commit processor.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Energy-efficient renaming with register versioning.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Accurately clustering moving objects with adaptive history filtering.
Proceedings of the 24th International Symposium on Computer and Information Sciences, 2009

Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures.
Proceedings of the ICPP 2009, 2009

MPTLsim: a simulator for X86 multicore processors.
Proceedings of the 46th Design Automation Conference, 2009

2008
Selective Writeback: Reducing Register File Pressure and Energy Consumption.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption.
IEEE Trans. Computers, 2008

Enhancing GridFTP performance using intelligent gateways.
Int. J. High Perform. Comput. Netw., 2008

Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessors.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Detecting and Tracking Spatio-temporal Clusters with Adaptive History Filtering.
Proceedings of the Workshops Proceedings of the 8th IEEE International Conference on Data Mining (ICDM 2008), 2008

DARE: A Framework for Dynamic Authentication of Remote Executions.
Proceedings of the Twenty-Fourth Annual Computer Security Applications Conference, 2008

2007
Low-Power Design and Temperature Management.
IEEE Micro, 2007

Securing Grid Data Transfer Services with Active Network Portals.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

hFS: a hybrid file system prototype for improving small file and metadata performance.
Proceedings of the 2007 EuroSys Conference, Lisbon, Portugal, March 21-23, 2007, 2007

2006
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency.
IEEE Trans. Computers, 2006

Early Register Deallocation Mechanisms Using Checkpointed Register Files.
IEEE Trans. Computers, 2006

Instruction packing: Toward fast and energy-efficient instruction scheduling.
ACM Trans. Archit. Code Optim., 2006

Register file caching for energy efficiency.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Selective writeback: exploiting transient values for energy-efficiency and performance.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors.
Proceedings of the High Performance Computing, 2006

SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005
An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers.
Proceedings of the Integrated Circuit and System Design, 2005

Improving Transaction Server Performance under Heavy Loads with Differentiated Service and Active Network Interfaces.
Proceedings of the Fourth IEEE International Symposium on Network Computing and Applications (NCA 2005), 2005

Incremental Commit Groups for Non-Atomic Trace Processing.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Instruction packing: reducing power and delay of the dynamic scheduling logic.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Real-Time Protection against DDoS Attacks Using Active Gateways.
Proceedings of the 25th International Conference on Distributed Computing Systems Workshops (ICDCS 2005 Workshops), 2005

Power-Efficient Wakeup Tag Broadcast.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Protecting grid data transfer services with active network interfaces.
Proceedings of the 6th IEEE/ACM International Conference on Grid Computing (GRID 2005), 2005

2004
Energy Efficient Comparators for Superscalar Datapaths.
IEEE Trans. Computers, 2004

Isolating Short-Lived Operands for Energy Reduction.
IEEE Trans. Computers, 2004

Complexity-Effective Reorder Buffer Designs for Superscalar Processors.
IEEE Trans. Computers, 2004

Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization.
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Increasing Processor Performance Through Early Register Release.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Maintaining useful server throughput under load attacks using active NIC portals.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

Fast Remote Isosurface Visualization With Chessboarding.
Proceedings of the 5th Eurographics/ACM SIGGRAPH Symposium on Parallel Graphics and Visualization, 2004

2003
Energy-efficient issue queue design.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Energy Efficient Register Renaming.
Proceedings of the Integrated Circuit and System Design, 2003

Power efficient comparators for long arguments in superscalar processors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Reducing reorder buffer complexity through selective operand caching.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Distributed Reorder Buffer Schemes for Low Power.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

yFS: A Journaling File System Design for Handling Large Data Sets with Reduced Seeking.
Proceedings of the FAST '03 Conference on File and Storage Technologies, March 31, 2003

Reducing Datapath Energy through the Isolation of Short-Lived Operands.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002
Energy-Efficient Design of the Reorder Buffer.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Low-complexity reorder buffer architecture.
Proceedings of the 16th international conference on Supercomputing, 2002

Multithreaded Isosurface Rendering on SMPs Using Span-Space Buckets.
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors.
Proceedings of the 2002 Design, 2002

2001
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Energy: efficient instruction dispatch buffer design for superscalar processors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Optimal Polling for Latency-Throughput Tradeoffs in Queue-Based Network Interfaces for Clusters.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000
Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999
Accelerating object-oriented applications using method lookup caches and register windowing.
J. Syst. Archit., 1999

Multi-Sensory Browser and Editor Model.
Proceedings of the 1999 ACM Symposium on Applied Computing, 1999

Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

A Fast Multithreaded Out-of-Core Visualization Technique.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

Post-Scheduling Optimization of Parallel Programs.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Designing Multiprocessor/Distributed Real-Time Systems Using the ASSERTS Toolkit.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Caching-Efficient Multithreaded Fast Multiplication of Sparse Matrices.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

A comparative study of some network subsystem organizations.
Proceedings of the 5th International Conference On High Performance Computing, 1998

1997
Energy-Efficiency of VLSI Caches: A Comparative Study.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Protected, low-latency message passing in the SNOW prototype.
Proceedings of the Fifth Euromicro Workshop on Parallel and Distributed Processing (PDP '97), 1997

Generalized cubic networks.
Proceedings of the Fifth Euromicro Workshop on Parallel and Distributed Processing (PDP '97), 1997

Analytical energy dissipation models for low-power caches.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

The Implementation of Low Latency Communication Primitives in the Snow Prototype.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

A comparison of two context allocation approaches for fast protected calls.
Proceedings of the Fourth International on High-Performance Computing, 1997

ASSERTS: a toolkit for real-time software design, development and evaluation.
Proceedings of the Ninth Euromicro Workshop on Real-Time Systems, 1997

1996
A Fast Capability Extension to a RISC Architecture.
Proceedings of the 22rd EUROMICRO Conference '96, 1996

Using Method Lookup Caches and Register Windowing to Speed Up Dynamically-Bound Object-Oriented Applications.
Proceedings of the 22rd EUROMICRO Conference '96, 1996

1995
Hierarchical Cubic Networks.
IEEE Trans. Parallel Distributed Syst., 1995

Bottom-Up Scheduling with Wormhole and Circuit Switched Routing.
Proceedings of the Languages, 1995

The Mcube: a symmetrical cube based network with twisted links.
Proceedings of IPPS '95, 1995

A Comparative Study of Single Hop WDM Interconnections for Multiprocessors.
Proceedings of the 9th international conference on Supercomputing, 1995

Static Message Combining in Task Graph Schedules.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

A Formal Study of the Mcube Interconnection Network.
Proceedings of the Euro-Par '95 Parallel Processing, 1995

1994
The architecture of response-pipelined content addressable memories.
Microprocess. Microprogramming, 1994

Response Pipelined CAM Chips: The First Generation and Beyond.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Scheduling Task Graphs Onto Distributed Memory Multiprocessors Under Realistic Constaints.
Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

OPTIMUL: A Hybrid Multiprocessor for Distributed and Shared Memory Multiprocessing with WDM Optical Fiber Interconnections.
Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

Improving Parallel Program Execution Time with Message Consolidation.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

A Bottom-Up Approach to Task Scheduling in Distributed Memory Multiprocessors.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Hybrid Multiprocessing in <i>OPTIMUL</i>: A Multiprocessor for Distributed and Shared Memory Multiprocessing with WDM Optical Fiber Interconnections.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993
Response-pipelined CAM chips - Building blocks for large associated arrays.
Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992
Scalable, Pipelined, Cmos VLSI Content Addressable Memory Chips - Architecture And Implementation.
Proceedings of the Fifth International Conference on VLSI Design, 1992

The time-constrained barrier synchronizer and its applications in parallel systems.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991
A high performance barrier synchronizer and its novel applications in highly parallel systems.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991

A Cache Coherency Mechanism with Limited Combining Capabilities for MIN-Based Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1991

Efficient Synchronization Schemes for Large-Scale Shared-Memory Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1991

1990
The Design and Evaluation of the Hierarchical Cubic Network.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989
The HCN: a versatile interconnection network based on cubes.
Proceedings of the Proceedings Supercomputing '89, Reno, NV, USA, November 12-17, 1989, 1989

1988
The capability mechanism of a VLSI processor.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988


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