Kanad Basu
Orcid: 0000-0002-6431-7512
According to our database1,
Kanad Basu
authored at least 116 papers
between 2008 and 2024.
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024
IEEE Trans. Very Large Scale Integr. Syst., June, 2024
DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
Bit-by-Bit: Investigating the Vulnerabilities of Binary Neural Networks to Adversarial Bit Flipping.
Trans. Mach. Learn. Res., 2024
Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning.
CoRR, 2024
CoRR, 2024
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
PristiQ: A Co-Design Framework for Preserving Data Security of Quantum Learning in the Cloud.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
Explainability to the Rescue: A Pattern-Based Approach for Detecting Adversarial Attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
MENDNet: Just-in-time Fault Detection and Mitigation in AI Systems with Uncertainty Quantification and Multi-Exit Networks.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Defense Against On-Chip Trojans Enabling Traffic Analysis Attacks Based on Machine Learning and Data Augmentation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators.
IEEE Trans. Computers, August, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Des. Test, April, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
IACR Cryptol. ePrint Arch., 2023
Bottlenecks in Secure Adoption of Deep Neural Networks in Safety-Critical Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits.
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
IEEE Trans. Emerg. Top. Comput., 2022
Real-Time Hardware-Based Malware and Micro-Architectural Attack Detection Utilizing CMOS Reservoir Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Explainable Machine Learning for Intrusion Detection via Hardware Performance Counters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Special Session: Effective In-field Testing of Deep Neural Network Hardware Accelerators.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Proceedings of the IEEE International Test Conference, 2022
Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Design and Logic Synthesis of a Scalable, Efficient Quantum Number Theoretic Transform.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Design and Analysis of a Scalable and Efficient Quantum Circuit for LWE Matrix Arithmetic.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
A Semi-formal Information Flow Validation for Analyzing Secret Asset Propagation in COTS IC Integrated Systems.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2021
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2021
ACM Trans. Embed. Comput. Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IACR Cryptol. ePrint Arch., 2021
Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Ultra-efficient Look-up Table based Programmable Processing in Memory Architecture for Data Encryption.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Inf. Forensics Secur., 2020
IEEE Trans. Inf. Forensics Secur., 2020
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Hardware-Assisted Detection of Firmware Attacks in Inverter-Based Cyberphysical Microgrids.
CoRR, 2020
CoRR, 2020
Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Analyzing the Efficiency of Machine Learning Classifiers in Hardware-Based Malware Detectors.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
ND-HMDs: Non-Differentiable Hardware Malware Detectors against Evasive Transient Execution Attacks.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
ACM Trans. Design Autom. Electr. Syst., 2019
IACR Cryptol. ePrint Arch., 2019
IEEE Des. Test, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Can Monitoring System State + Counting Custom Instruction Sequences Aid Malware Detection?
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2018
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018
2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
RTL level trace signal selection and coverage estimation during post-silicon validation.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017
2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
2012
CoRR, 2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Efficient combination of trace and scan signals for post silicon validation and debug.
Proceedings of the 2011 IEEE International Test Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
2008
A novel test-data compression technique using application-aware bitmask and dictionary selection methods.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008