Kamran Saleh

According to our database1, Kamran Saleh authored at least 5 papers between 2005 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2007
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
High-Level Optimization of Asynchronous Systems Utilizing Conditional Restructuring.
Proceedings of the International Symposium on System-on-Chip, 2006

2005
Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005


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