Kamalika Datta

Frontiers Comput. Sci., December, 2024

ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., November, 2024

qSAT: Design of an Efficient Quantum Satisfiability Solver for Hardware Equivalence Checking.

[BibT_eX]

[DOI]

Mohammed E. Djeridane

Lennart Weingarten

CoRR, 2024

In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures.

[BibT_eX]

[DOI]

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Exploring the Potential of Dynamic Quantum Circuit for Improving Device Scalability.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Is Simulation the only Alternative for Effective Verification of Dynamic Quantum Circuits?

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 16th International Conference, 2024

Design Automation Challenges and Benefits of Dynamic Quantum Circuit in Present NISQ Era and Beyond: (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Complete and Efficient Verification for a RISC-V Processor Using Formal Verification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Dynamic Realization of Multiple Control Toffoli Gate.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Impact of sneak paths on in-memory logic design in memristive crossbars.

[BibT_eX]

[DOI]

it Inf. Technol., May, 2023

Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 15th International Conference, 2023

Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 15th International Conference, 2023

Verification of In-Memory Logic Design using ReRAM Crossbars.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor.

[BibT_eX]

[DOI]

Lennart Weingarten

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Memristors: Device Modeling, Design and Verification.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Feed-Forward learning algorithm for resistive memories.

[BibT_eX]

[DOI]

Dev Narayan Yadav

J. Syst. Archit., 2022

CoMIC: Complementary Memristor based in-memory computing in 3D architecture.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

In-Memory Computing on Resistive RAM Systems Using Majority Operation.

[BibT_eX]

[DOI]

F. Lalchhandama

Mukesh Sahani

Vompolu Mohan Srinivas

J. Circuits Syst. Comput., 2022

FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications.

[BibT_eX]

[DOI]

Dev Narayan Yadav

J. Electron. Test., 2022

Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture.

[BibT_eX]

[DOI]

Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

Mapping Quantum Circuits to 2-Dimensional Quantum Architectures.

[BibT_eX]

[DOI]

Proceedings of the 52. Jahrestagung der Gesellschaft für Informatik, INFORMATIK 2022, Informatik in den Naturwissenschaften, 26., 2022

SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library.

[BibT_eX]

[DOI]

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles.

[BibT_eX]

[DOI]

Saeideh Shirinzadeh

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2020

Improved Mapping of Quantum Circuits to IBM QX Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Improved Ternary Reversible Logic Synthesis Using Group Theoretic Approach.

[BibT_eX]

[DOI]

P. Mercy Nesa Rani

J. Circuits Syst. Comput., 2020

An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD).

[BibT_eX]

[DOI]

Integr., 2020

Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Fledge: Flexible Edge Platforms Enabled by In-memory Computing.

[BibT_eX]

[DOI]

Jackson Chun-Yang Huang

Aaron Thean

Mohamed M. Sabry Aly

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Efficient Design of Quantum Circuits Using Nearest Neighbor Constraint in 3D Architecture.

[BibT_eX]

[DOI]

Leniency Marbaniang

J. Circuits Syst. Comput., 2019

Look-ahead mapping of Boolean functions in memristive crossbar array.

[BibT_eX]

[DOI]

Dev Narayan Yadav

Integr., 2019

Mapping of Boolean Logic Functions onto 3D Memristor Crossbar.

[BibT_eX]

[DOI]

Naveen Murali G

Peddireddi Satya Vardhan

F. Lalchhandama

Yaswanth Krishna Yadav Danaboina

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Design and Implementation of Threshold Logic Functions Using Memristors.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Exploiting Negative Control Lines and Nearest Neighbor for Improved Comparator Design.

[BibT_eX]

[DOI]

Tathagato Bose

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A staircase structure for scalable and efficient synthesis of memristor-aided logic.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar.

[BibT_eX]

[DOI]

Rahul Gharpinde

IEEE Trans. Very Large Scale Integr. Syst., 2018

Efficient Mapping of Boolean Functions to Memristor Crossbar Using MAGIC NOR Gates.

[BibT_eX]

[DOI]

Rahul Gharpinde

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Scalable in-memory mapping of Boolean functions in memristive crossbar array using simulated annealing.

[BibT_eX]

[DOI]

J. Syst. Archit., 2018

Generalizing the Concept of Scalable Reversible Circuit Synthesis for Multiple-Valued Logic.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Logic Design Using Memristors: An Emerging Technology.

[BibT_eX]

[DOI]

Saeideh Shirinzadeh

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Fast In-Memory Computation of Boolean Functions in Memristive Crossbar Array.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

Modelling and Simulation of Non-Ideal MAGIC NOR Gates on Memristor Crossbar.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017

Exact Synthesis of Reversible Logic Circuits using Model Checking.

[BibT_eX]

[DOI]

Rajarshi Ray

Arup Deka

CoRR, 2017

Improved NCV Gate Realization of Arbitrary Size Toffoli Gates.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Improved Decomposition of Multiple-Control Ternary Toffoli Gates Using Muthukrishnan-Stroud Quantum Gates.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 9th International Conference, 2017

Design of Efficient Quantum Circuits Using Nearest Neighbor Constraint in 2D Architecture.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 9th International Conference, 2017

Test Pattern Generation Effort Evaluation of Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 9th International Conference, 2017

Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates.

[BibT_eX]

[DOI]

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

2016

A Heuristic for Linear Nearest Neighbor Realization of Quantum Circuits by SWAP Gate Insertion Using N-Gate Lookahead.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

An Improved Approach for the Synthesis of Boolean Functions Using Memristor Based IMPLY and INVERSE-IMPLY Gates.

[BibT_eX]

[DOI]

F. Lalchhandama

Brojo Gopal Sapui

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Parameter sensing and object tracking using global positioning system.

[BibT_eX]

[DOI]

Arghya P. Saikia Thengal

Naman Rastogi

Abhilash Medhi

Ritu Ranjan Shrivastwa

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

An improved gate library for logic synthesis of optical circuits.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Area efficient implementation of ripple carry adder using memristor crossbar arrays.

[BibT_eX]

[DOI]

Rahul Gharpinde

Varun Chowdhary Paturi

Proceedings of the 11th International Design & Test Symposium, 2016

2015

A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines.

[BibT_eX]

[DOI]

Hafizur Rahaman

IEEE Trans. Computers, 2015

All optical design of binary adders using semiconductor optical amplifier assisted Mach-Zehnder interferometer.

[BibT_eX]

[DOI]

Tanay Chattopadhyay

Microelectron. J., 2015

BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 7th International Conference, 2015

Fast Qubit Placement in 2D Architecture Using Nearest Neighbor Realization.

[BibT_eX]

[DOI]

Ritu Ranjan Shrivastwa

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014

An Approach to Reversible Logic Synthesis Using Input and Output Permutations.

[BibT_eX]

[DOI]

Trans. Comput. Sci., 2014

An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

All Optical Reversible Multiplexer Design Using Mach-Zehnder Interferometer.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

RevVis: Visualization of Structures and Properties in Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 6th International Conference, 2014

BDD based synthesis of Boolean functions using memristors.

[BibT_eX]

[DOI]

Sayak Chakraborti

Paturi Varun Chowdhary

Proceedings of the 9th International Design and Test Symposium, 2014

Optimizing DD-based synthesis of reversible circuits using negative control lines.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

An ESOP-Based Reversible Circuit Synthesis Flow Using Simulated Annealing.

[BibT_eX]

[DOI]

Proceedings of the Applied Computation and Security Systems - ACSS 2014, 2014

2013

Partial encryption and watermarking scheme for audio files with controlled degradation of quality.

[BibT_eX]

[DOI]

Multim. Tools Appl., 2013

Particle Swarm Optimization Based Reversible Circuit Synthesis Using Mixed Control Toffoli Gates.

[BibT_eX]

[DOI]

Hafizur Rahaman

J. Low Power Electron., 2013

Exploiting Negative Control Lines in the Optimization of Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 5th International Conference, 2013

ESOP-Based Synthesis of Reversible Circuit Using Improved Cube List.

[BibT_eX]

[DOI]

Chandan Bandyopadhyay

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

An evolutionary approach to reversible logic synthesis using output permutation.

[BibT_eX]

[DOI]

Proceedings of the 8th International Design and Test Symposium, 2013

Reversible logic implementation of AES algorithm.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2012

Synthesis of Reversible Circuits Using Heuristic Search Method.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

Particle Swarm Optimization Based Circuit Synthesis of Reversible Logic.

[BibT_eX]

[DOI]