Kairang Chen

According to our database, Kairang Chen authored at least 6 papers between 2015 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

On First-Order Compensation of Timing Mismatch in Two-Channel TIADCs.

Yinan Wang, Xiangyu Liu, Håkan Johansson, Chengxuan Zhao, Kairang Chen, Xi Zhu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

A Linearity-Improved 8-bit 320-MS/s SAR ADC With Metastability Immunity Technique.

Daiguo Xu, Lei Qiu, Zhengping Zhang, Tao Liu, Lu Liu, Kairang Chen, Shiliu Xu

IEEE Trans. Very Large Scale Integr. Syst., 2018

2016

Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS.

Kairang Chen, Martin Nielsen-Lönn, Atila Alvandpour

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Design of a gain-stage for pipelined SAR ADC using capacitive charge pump.

Kairang Chen, Atila Alvandpour

Proceedings of the 2016 MIXDES, 2016

Capacitive charge pump gain-stage with source follower buffers for pipelined SAR ADCs.

Kairang Chen, Atila Alvandpour

Proceedings of the International Symposium on Integrated Circuits, 2016

2015

Power analysis for two-stage high resolution pipeline SAR ADC.

Kairang Chen, Quoc-Tai Duong, Atila Alvandpour

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015