Kailash Chandrashekar
According to our database1,
Kailash Chandrashekar
authored at least 15 papers
between 2008 and 2021.
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Bibliography
2021
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2021
2020
25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2017
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
2013
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.
IEEE J. Solid State Circuits, 2013
2012
A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS.
IEEE J. Solid State Circuits, 2012
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A digital fractional-N PLL with a 3mW 0.004mm<sup>2</sup> 6-bit PVT and mismatch insensitive TDC.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
2010
A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precision.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008