Kaifeng Xu
According to our database1,
Kaifeng Xu
authored at least 9 papers
between 2008 and 2024.
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Bibliography
2024
MindPalace: A Framework for Studying Microarchitecture Design of Function-as-a-Service.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024
2023
DECADES: A 67mm<sup>2</sup>, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
CIFER: A 12nm, 16mm<sup>2</sup>, 22-Core SoC with a 1541 LUT6/mm<sup>2</sup> 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2014
Proceedings of the Advances in Wireless Sensor Networks - The 8th China Conference, 2014
2010
Proceedings of the Web Information Systems Engineering - WISE 2010, 2010
Proceedings of the ISWC 2010 Posters & Demonstrations Track: Collected Abstracts, 2010
2009
Proceedings of the ACM SIGMOD International Conference on Management of Data, 2009
2008
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2008
Proceedings of the Semantic Web, 3rd Asian Semantic Web Conference, 2008