Kai Zhang

According to our database, Kai Zhang authored at least 16 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

FT-Matrix: A Coordination-Aware Architecture for Signal Processing.

Shuming Chen, Yaohua Wang, Sheng Liu, Jianghua Wan, Haiyan Chen, Hengzhu Liu, Kai Zhang, Xiangyuan Liu, Xi Ning

IEEE Micro, 2014

2013

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures.

Yaohua Wang, Shuming Chen, Hu Chen, Jianghua Wan, Kai Zhang, Sheng Liu

IEICE Trans. Inf. Syst., 2013

Breaking the performance bottleneck of sparse matrix-vector multiplication on SIMD processors.

Kai Zhang, Shuming Chen, Yaohua Wang, Jianghua Wan

IEICE Electron. Express, 2013

A novel QPP interleaver for parallel turbo decoder.

Wei Liu, Shuming Chen, Hu Chen, Yaohua Wang, Sheng Liu, Kai Zhang, Xi Ning

IEICE Electron. Express, 2013

A Fine-Grained Pipelined Implementation of LU Decomposition on SIMD Processors.

Kai Zhang, Shuming Chen, Wei Liu, Xi Ning

Proceedings of the Network and Parallel Computing - 10th IFIP International Conference, 2013

Redefining the relationship between scalar and parallel units in SIMD architectures.

Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments.

Yaohua Wang, Shuming Chen, Jianghua Wan, Jiayuan Meng, Kai Zhang, Wei Liu, Xi Ning

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors.

Kai Zhang, Shuming Chen, Hu Chen, Yaohua Wang, Xiaowen Chen, Sheng Liu, Wei Liu

IEICE Electron. Express, 2012

A cost conscious performance model for media processors.

Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Hu Chen, Sheng Liu, Xi Ning

IEICE Electron. Express, 2012

Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures.

Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Xiaowen Chen, Hu Chen, Haibo Wang

IEEE Comput. Archit. Lett., 2012

Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes.

Yaohua Wang, Shuming Chen, Kai Zhang, Hu Chen, Xiaowen Chen

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Architectural Implications for SIMD Processors in the Wireless Communication Domain.

Yaohua Wang, Kai Zhang, Jianghua Wan, Sheng Liu, Xi Ning, Shuming Chen

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011

LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs.

Sheng Liu, Shuming Chen, Xi Ning, Jianghua Wan, Hu Chen, Kai Zhang, Yaohua Wang

IEICE Electron. Express, 2011

SUCA: a scalable unicore architecture with novel instruction encoding and distributed execution control.

Hu Chen, Shuming Chen, Yaohua Wang, Kai Zhang

IEICE Electron. Express, 2011

AIFSP: An Adaptive Instruction Flow Stream Processor.

Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang, Shenggang Chen

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs.

Kai Zhang, Shuming Chen, Sheng Liu, Yaohua Wang, Junhui Huang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011