Kai Yu

Affiliations:
  • Intel Corporation, Hillsboro, OR, USA
  • Carnegie Mellon University, Pittsburgh, PA, USA (PhD 2009)


According to our database1, Kai Yu authored at least 8 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2022
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET.
IEEE J. Solid State Circuits, 2022

2021
8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET.
IEEE J. Solid State Circuits, 2019

2018
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2015
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014


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