Kai-Wei Hong

According to our database, Kai-Wei Hong authored at least 8 papers between 2006 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing.

Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, Bo-Qian Jiang

IEEE Trans. Very Large Scale Integr. Syst., 2012

2011

Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator.

Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong

IEEE Trans. Very Large Scale Integr. Syst., 2011

A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit.

Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

A loading effect insensitive and high precision clock synchronization circuit.

Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, Chien-Cheng Chen

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters.

Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee

J. Circuits Syst. Comput., 2009

A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application.

Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo

IEICE Trans. Electron., 2009

2008

A low jitter self-calibration PLL for 10Gbps SoC transmission links application.

Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006

A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay.

Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang

Proceedings of the 13th IEEE International Conference on Electronics, 2006