Kai-Pui Lam

Chi-Sang Poon

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC.

[BibT_eX]

[DOI]

Chi-Sang Poon

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

On-chip dynamic programming networks using 3D-TSV integration.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

2010

A CMOS Current-Mode Dynamic Programming Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009

Intra-daily information of range-based volatility for MEM-GARCH.

[BibT_eX]

[DOI]

Math. Comput. Simul., 2009

A DP-network for optimal dynamic routing in network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2007

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Networks-on-Chips, 2007

A Current-Mode Analog Circuit for Reinforcement Learning Problems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

How Does Sample Size Affect GARCH Models?

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

2004

On Computing Maximum Likelihood Phylogeny Using FPGA p.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA.

[BibT_eX]

[DOI]

Proceedings of the 3rd International IEEE Computer Society Computational Systems Bioinformatics Conference, 2004

2003

Analog and digital FPGA implementation of BRIN for optimization problems.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 2003

Field programmable gate arrays and analog implementation of BRIN for optimization problems.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An FPGA-based eigenfilter using fast Hebbian learning.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE Computer Society Bioinformatics Conference, 2003

2002

Extracting Causation Knowledge from Natural Language Texts.

[BibT_eX]

[DOI]

Proceedings of the Advances in Knowledge Discovery and Data Mining, 2002

Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

1996

A binary relation inference network Part 1. General concepts.

[BibT_eX]

[DOI]

Crystal J. Su

Int. J. Syst. Sci., 1996

A continuous-time inference network and its hybrid implementations.

[BibT_eX]

[DOI]

Int. J. Syst. Sci., 1996

A binary relation inference network Part 2. State-space techniques.

[BibT_eX]

[DOI]

Int. J. Syst. Sci., 1996

1993

Digital Circuit Implementation of a Continuous-time Inference Network for the Transitive Closure Problem.

[BibT_eX]

Crystal J. Su

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991

On a Binary Relation Inference Network.

[BibT_eX]

[DOI]