Kai Li
Orcid: 0000-0003-3251-931XAffiliations:
- Southern University of Science and Technology, School of Microelectronics, Shenzhen, Guangdong, China
According to our database1,
Kai Li
authored at least 17 papers
between 2021 and 2024.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
IEEE Open J. Circuits Syst., 2024
EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models.
CoRR, 2024
LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024
A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2022
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Multiple-Precision Floating-Point Dot Product Unit for Efficient Convolution Computation.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021